FIG. 1 is a schematic diagram of a conventional data discrimination unit including a slice amplifier. In FIG. 1, an input signal S.sub.in is first received by a slice amplifier 11. The slice amplifier 11 constitutes, together with a wave reshaping part 12 following the amplifier 11, a data discrimination unit 10. The input signal S.sub.in is an analog signal having the waveforms as shown, and each waveform represents a data logic "0" or "1". Although the waveforms have already passed through an equalizer (not shown), each waveform still has a peak shape. Whether each mountain-shaped waveform represents a data logic "0" or "1" is determined by a waveform reshaping part 12, which is comprised of a D-flip flop (FF) for sampling each waveform by using a constant clock CLK. In this case, of course, the inherent digital output data D.sub.out can be reproduced if the waveform is correctly sampled by the clock CLK. If, however, the phase deviation occurs in the clock CLK, the clock timing cannot be aligned with the top of each peak of the waveform, and therefore, the clock samples the valley portion between the two adjacent peak waveforms, and thus a discrimination error is produced.
To overcome the problem of phase deviation, the waveform of the input signal S.sub.in is sliced at a certain level, for example, a level TH, and the thus-sliced signal is then transformed into a rectangular-shaped waveform signal which is an output signal S.sub.out. Therefore, the data logic "1" can be correctly sampled even if there is a more or less phase deviation of the clock. Namely, the slice amplifier 11 achieves the aforesaid transformation of the signal, i.e., S.sub.in .fwdarw.S.sub.out.
FIG. 2 is a circuit diagram illustrating an example of a prior art slice amplifier. The prior art slice amplifier 11 is comprised of a first bipolar transistor Q.sub.1 receiving the input signal S.sub.in at its base, a second bipolar transistor Q.sub.2 receiving a reference voltage V.sub.ref at its base, and producing the output signal S.sub.out, and a constant current source CS, and thus forms, as a whole, a current switch.
The prior art slice amplifier of the bipolar transistor type shown in FIG. 2 can not cope with very high speed data transmission because, due to the operation limit of the bipolar transistor per se, the slice amplifier is limited to a data transmission maximum speed on the order of 500 Mb/s.
The present invention is based on the employment of a field effect transistor (FET), instead of the bipolar transistor, to abolish this operation limit. For example, a GaAs.multidot.FET or a high electron mobility transistor, so-called HEMT, can raise the operation limit up to the order of several G b/s. In view of this, the inventors have attempted to replace the bipolar transistors Q.sub.1 and Q.sub.2 in the slice amplifier with FETs.
FIG. 3 is a circuit diagram of a prototype slice amplifier using FETs. The slice amplifier 21 contains the FETs T.sub.1 and T.sub.2, instead of the bipolar transistors Q.sub.1 and Q.sub.2 contained in the slice amplifier 11. Note, the meanings of the characters S.sub.in (input signal), S.sub.out (output signal, i.e., sliced signal), CS (constant current source), and so on have been already explained.
The inventors, however, found that the slice amplifier 21 cannot be practically used. This is because, first, the variance of the pinch-off voltage (V.sub.p) of each FET is too large, that is, the FETs have different pinch-off voltage (V.sub.p) to each other, and second, the pinch-off voltage (V.sub.p) per se is susceptible to variations of temperature.
FIG. 4 depicts characteristic curves in the I.sub.D -V.sub.GS of an FET. This characteristic curve is typical for a usual FET. When the input signal S.sub.in is applied to the gate of the FET, the hatching portion thereof is cut away if the related FET has the characteristic curve I. Alternatively, if another FET having the characteristic curve II is used, the whole of the signal S.sub.in will be cut away. In general, the FET exhibits a characteristic curve, i.e., I.sub.D -V.sub.GS, which is analogous to that of a vacuum tube. In this case, the gate-source voltage V.sub.GS at the drain current I.sub.D of zero, i.e., the aforesaid pintch-off voltage, varies, in actuality, over a range as large as 1V through 4V in each FET. Due to this nonuniformity of the I.sub.D -V.sub.GS characteristics, it is almost impossible to realize a current switch available for a slice amplifier. In the circumstance, it may be possible to eliminate the nonuniformity of the I.sub.D -V.sub.GS characteristics by fabricating FETs on the same semiconductor chip in the form of an integrated circuit (IC). But, the slice amplifier is not inherently expected to be mass produced, and therefore, a problem arises in that the cost of the slice amplifier will increase due to the employment of the IC process.
Further, as another disadvantage, the pinch-off voltage is also susceptible to variations of temperature.
FIG. 5 depicts characteristic curves in the I.sub.D -V.sub.GS of an FET in relation to a temperature variation. In FIG. 5, curves III, IV, and V represent I.sub.D -V.sub.GS characteristics obtained at a low temperature, a median temperature (room temperature) and a high temperature. It is apparent that the curves are not uniform, and that the pinch-off voltage V.sub.p varies accordingly. Thus, the output signal S.sub.out with respect to the input signal S.sub.in is not stable.
A similar variation of the pinch-off voltage V.sub.p also occurs in response to a variation of a power source voltage.